The present invention relates generally to the fabrication of dynamic random access memories (DRAM), and more particularly to DRAM stacked cell capacitor (STC) contacts in a capacitor-over-bit line (COB) DRAM cell structure.
The drive for increasing DRAM densities has given rise to a number of different DRAM cell configurations. One way in which to classify DRAM cells having capacitors formed above the substrate, is to designate the vertical position (layer) of the storage capacitor relative to the vertical position (layer) of the bit line. This gives rise to two, general, self-descriptive groups; bit line-over-capacitor (BOC) cells, and capacitor-over-bit line (COB) cells. For BOC cells, the bit line contact is formed by etching a contact hole after the storage capacitor has been formed. As a result, the location of the bit line can limit the lateral extent of the storage capacitor. An example of a BOC cell is set forth in xe2x80x9c3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMSxe2x80x9d by Ema et al. appearing in IEDM 1988, pp. 592-595. The BOC cell appears in FIG. 1 of Ema et al. Other examples of BOC cells are set forth in U.S. Pat. No. 5,504,704 entitled SEMICONDUCTOR MEMORY DEVICE and issued to Sato et al. on Apr. 2, 1996, U.S. Pat. No. 5,188,975 entitled METHOD OF PRODUCING A CONNECTION HOLE FOR A DRAM HAVING AT LEAST THREE CONDUCTOR LAYERS IN A SELF ALIGNMENT MANNER issued to Kojima et al. on February, and in xe2x80x9cFully Self-Aligned 6F2 Cell Technology for Low Cost 1 Gb DRAMxe2x80x9d by Aoki et al. appearing in 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 22-23.
Unlike most BOC cells, COB cells provide more lateral room for the location of the storage capacitor. An illustration contrasting a COB cell with a BOC cell is set forth in FIG. 11 of Ema et al. The capacitor of the COB cell extends over both the access transistor gate and the bit line, and is limited in the lateral direction only by the adjacent storage capacitor.
Examples of other COB cells are disclosed in U.S. Pat. No. 5,428,235 entitled SEMICONDUCTOR MEMORY DEVICE INCLUDING IMPROVED CONNECTION STRUCTURE TO FET ELEMENTS and issued to Shimizu et al. on Jun. 27, 1995, U.S. Pat. No. 5,231,043 entitled CONTACT ALIGNMENT FOR INTEGRATED CIRCUITS issued to Chan et al. on Jul. 27, 1996, and in U.S. Pat. No. 5,053,351 entitled METHOD OF MAKING STACKED E-CELL CAPACITOR DRAM CELL issued to Fazan et al. on Oct. 1, 1991.
As DRAM densities continue to shrink, more complex manufacturing processes utilizing multiple conductive layers are needed to achieve acceptable cell capacitance while reducing DRAM cell size. This requires minimum tolerances in the placement of contacts and/or vias with respect to underlying conductive layers. Despite minimum tolerances, the possibility of unwanted shorts between the contact/vias and underlying layers is eliminated by ensuring that sufficient interlayer dielectric thickness exists therebetween. In order to reduce such tolerances, it is known in the prior art to use self-alignment techniques for both BOC and COB cells. Self-alignment techniques typically ensure that lower conductive layers are sufficiently insulated so as to allow for the overlap of a subsequently etched contact hole or via. For example, in the Kojima et al. patent and the Aoki et al. article, both the capacitor contacts and the bit line are self-aligned with the word lines. In both of these cases the word lines are isolated by a top dielectric and sidewall dielectrics. In the Chan et al. patent, differential dielectric deposition techniques followed by a blanket anisotropic etch, are used to form a self-aligned capacitor contact.
Commonly owned, copending U.S. patent application Ser. No. 08/456,090 discloses a BOC DRAM cell having a capacitor contact that is self-aligned with a word line, and provides increased capacitance.
Increasing the number of self-aligned steps used in the fabrication of an integrated circuit reduces the constraints on the placement of underlying layers, allowing for more compact designs and thus higher densities.
It is an object of the present invention to provide DRAM cell with reduced cell area.
It is another object of the present invention to provide a DRAM cell having increased capacitance.
It is another object of the present invention to provide a COB DRAM cell having greater tolerances for placement of the capacitor contact.
A preferred embodiment of the present invention is a DRAM memory cell having an access transistor and storage capacitor. The DRAM cell has a COB configuration with the storage capacitor contact being simultaneously self-aligned with the bit line and word line of the cell. Word lines and bit lines are formed with an insulating structure that includes a top dielectric layer and sidewall dielectric spacers. An etch stop layer is formed over the word lines and the drains of the access transistors. Interlayer dielectrics (ILDs) provide vertical isolation of the word lines from the bit lines, and the bit lines from the storage capacitor. The etch used to clear the self-aligned capacitor contact hole includes a first etch, selective to the etch stop layer, which clears a contact hole down to the etch stop layer. The etch stop layer protects the word lines from the first etch. A second etch, selective to the ILDs is used to clear the access transistor source surface. The bit lines and the word lines are protected from the second etch by their respective insulating structures. The capacitor storage node is then formed that is self-aligned with the access transistor source.
According to one aspect of the present invention, the first etch layer and the insulating structure surrounding the bit lines are composed of silicon nitride, and the insulating structure surrounding the word lines and the ILD layers is composed of silicon dioxide. The first etch is selective to silicon nitride, and the second etch step is selective to silicon dioxide.
According to another aspect of the present invention, the insulating structure surrounding the word lines includes a first top layer of silicon dioxide, sidewall spacers of silicon dioxide, and a second layer top layer of silicon nitride.
An advantage of the present invention is that it provides a DRAM cell with a capacitor contact that is self-aligned with the array bit lines and word lines.
Another advantage of the present invention is that it provides a DRAM cell with a capacitor of increased capacitance that has a contact that is self-aligned with the bit line and the word line.
Another advantage of the present invention is that it provides a DRAM cell having a self-aligned capacitor contact that can be formed utilizing conventional capacitor contact masks.
Other objects and advantages of the present invention will become apparent in light of the following description thereof.